AMD has registered a patent describing a GPU chiplet design feature (of multiple crystals). Specifically, the new patent called Active Bridge Chiplet With Integrated Cache describes an active bus with integrated cache memory. We can assume that this is an evolution of Infinity Cache technology, which first appeared in Radeon RX 6000 series video cards.
The idea of AMD is to entrust the interface which connects individual GPU chipsets with the role of third level cache memory. Recall that in current GPUs based on RDNA 2 architecture the role of layer 3 cache is performed by Infinity Cache.
Block diagram showing the processing system using an active bus connecting GPU chipsets
AMD explains in the patent that any interaction between the chipsets will be via an active bus, which will be required to access the memory channels on individual GPU chips. Instead of relying on the individual caches of each chiplet, AMD proposes to use the active bus cache as a monolithic cache for the GPU. In other words, the cache memory will be addressed as a single registry.
Block diagram of the GPU chipset cache hierarchy unified by an active chipset bus
AMD's latest patent, as well as the previous one reported in January this year, indicates that the company is actively exploring the use of multi-chiplet GPUs in the future. True, it is not clear yet whether it is only a question of next-generation computational gas pedals on CDNA architecture or AMD is considering using chiplet design in consumer video cards on RDNA architecture as well.
Block diagram of three-chiplet configuration
Schematic of the method of data exchange between chipsets
By the way, not only AMD is working in this direction. For example, there is a similar development at Intel and NVIDIA. The first has a huge multichip He-HPC, the second & ; GH100 (Hopper ), which is also attributed a multichip assembly (MCM).