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AMD announced EPYC Milan-X processors with 3D V-Cache: 804 MB of cache and 64 Zen3 cores

AMD announced EPYC Milan-X processors with 3D V-Cache: 804 MB of cache and 64 Zen3 cores

AMD has announced its series of server processors codenamed Milan-X. The new products are the evolution of EPYC 7003 (Milan), introduced this spring, and are designed primarily for high-performance computing (HPC). The main difference from "regular" Milan will be significantly increased amount of cache-memory, which allowed AMD to call its processors the fastest in the world.

Where does the 804 MB figure come from? The math is simple. Each Zen3 core has 32 Kbytes of L1 cache for instructions and data + 512 Kbytes of L2 cache. The eight cores in the CCX complex have 32 Mbytes of the total L3 cache. This is in addition to 64 MB of 3D V-Cache & ; the maximum configuration of 8 CCX cores results in a total of 768 MB of 3D V-Cache in addition to the underlying cache hierarchy. Thus, exactly by this parameter the record of IBM z15 is broken, though this CPU is oriented for absolutely different tasks. But among x86-64 there are no equal to Milan-X now. Moreover, according to AMD, 3D V-Cache implementation is currently unique in the industry. Additional cache has direct connection to CCX via copper channels, what allows to significantly increase packing density and power efficiency, reduce delays and improve thermal performance. However, detailed V-Cache specifications are not given yet.

Importantly, the new products will be compatible with existing SP3 platforms for Milan, which will simplify testing and validation & ; a BIOS update will be released for them. Alas, the company doesn't give any data on frequencies, TDP or price yet & ; the Milan-X release is scheduled for Q1 2022. But the footnotes to the presentation, in particular, mention not only 64-core Milan-X, but also 16-core. We must assume that such «sandwiches» will be more expensive than conventional CCX, because here the scrap price will be higher. Also, compatibility with existing software is announced, but the developers are already actively working to further optimize their solutions. The biggest benefit from the increased cache will be loads that are critical for the memory speed and access latency. Among them AMD mentions finite element method, structural analysis, computational fluid dynamics and automated electronics design systems (EDA). For the latter, using Synopsys VCS as an example, the performance growth was 66%.

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