Summer leak of specs of future AMD EPYC Genoa server processors based on Zen4 architecture is getting more and more confirmed. A month ago, AMD officially announced that these CPUs will get up to 96 cores, which is one and a half times more than the EPYC Milan/Rome. And recently released Linux kernel patches showed that «models 10h-1Fh and A0h-AFh of 19h» family will have up to 12 CCD. They also showed that the memory channels of new processors will also be one and a half times as many & ; 12.
Today ComputerBase has shared a table with possible memory module configurations. From this table we see that new processors will support DDR5-5200, not only as single-ring RDIMMs, but also quad- or octa-range LRDIMMs. To tell the truth, in the last case when using mass 128 GB modules the maximum memory capacity per socket will not exceed 1.5 TB.
However, if you believe the table, DDR5-5200 will only be available in 1DPC mode (one module per channel) and only with more expensive memory. And in the case of 2DPC the limit will already be DDR5-4800. And now it is difficult to say whether the memory in this mode will work at higher frequencies (as it was in practice with Milan), since the requirements for board wiring and signal integrity have become much higher, which, by the way, will affect their price.
If it is not the speed that is important, but the volume, then with 16 ranked (it is strictly 3DS RDIMM) DDR5-4000 modules in 2DPC mode you can get as much as 12 TB of RAM. This would require 512 GB modules. These, for example, are being prepared by Samsung. However, implementation of CXL support by new AMD and Intel server platforms in the future will potentially simplify the growth of available memory size for servers in exchange for some reduction of its speed and increase of delays. It remains to be seen how many PCIe 5.0 lanes will actually get EPYC Genoa and how many of them will support CXL.